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3 volt intel ? strataflash? memory 28f128j3a, 28F640J3A, 28f320j3a (x8/x16) product preview datasheet product features capitalizing on intels 0.25 generation two-bit-per-cell technology, second generation intel ? strataflash? memory products provide 2x the bits in 1x the space, with new features for mainstream performance. offered in 128-mbit (16-mbyte), 64-mbit, and 32-mbit densities, these devices bring reliable, two-bit-per-cell storage technology to the flash market segment. benefits include: more density in less space, high-speed interface, lowest cost-per-bit nor devices, support for code and data storage, and easy migration to future devices. using the same nor-based etox? technology as intels one-bit-per-cell products, intel strataflash memory devices take advantage of over 700 million units of manufacturing experience since 1987. as a result, intel strataflash components are ideal for code and data applications where high density and low cost are required. examples include networking, telecommunications, digital set top boxes, audio recording, and digital imaging. by applying flashfile? memory family pinouts, intel strataflash memory components allow easy design migrations from existing word-wide flashfile memory (28f160s3 and 28f320s3), and first generation intel strataflash memory (28f640j5 and 28f320j5) devices. intel strataflash memory components deliver a new generation of forward-compatible software support. by using the common flash interface (cfi) and the scaleable command set (scs), customers can take advantage of density upgrades and optimized write capabilities of future intel strataflash memory devices. manufactured on intel ? 0.25 micron etox? vi process technology, intel strataflash memory provides the highest levels of quality and reliability. n high-density symmetrically-blocked architecture 128 128-kbyte erase blocks (128 m) 6 4 128-kbyte erase blocks (64 m) 32 128-kbyte erase blocks (32 m) n high performance interface asynchronous page-mode reads 100/25 ns read access time (32 m) 120/25 ns read access time (64 m) 150/25 ns read access time (128 m) n 2.7 vC3.6 v v cc operation 2.7 vC 3.6 v and 5 v i/o capable n 128-bit protection register 64-bit unique device identifier 64-bit user programmable otp cells n enhanced data protection features absolute protection with v pen = gnd flexible block locking block erase/program lockout during power transitions n packaging 56-lead tsop package 64-ball intel ? easy bga package n cross-compatible command support intel basic command set common flash interface scaleable command set n 32-byte write buffer 6 s per byte effective programming time n 12,800,000 total erase cycles (128 m) 6,400,000 total erase cycles (64 m) 3,200,000 total erase cycles (32 m) 100,000 erase cycles per block n automation suspend options block erase suspend to read block erase suspend to program program suspend to read n 0.25 intel ? strataflash? memory technology order number: 290667-001 july 1999 notice: this datasheet contains information on products in the design phase of development. do not finalize a design with this information. revised information will be published when the product becomes available. verify with your local intel sales office that you have the latest datasheet before finalizing a design .
product preview information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the 28f128j3a, 28F640J3A, 28f320j3a may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1999 *other brands and names are the property of their respective owners.
product preview iii 28f128j3a, 28F640J3A, 28f320j3a contents 1.0 product overview .............................................................................................. 1 2.0 principles of operation ............................................................................... 5 2.1 data protection...................................................................................................... 6 3.0 bus operation ....................................................................................................... 6 3.1 read...................................................................................................................... 8 3.2 output disable....................................................................................................... 8 3.3 standby ................................................................................................................. 8 3.4 reset/power-down ............................................................................................... 8 3.5 read query ........................................................................................................... 9 3.6 read identifier codes............................................................................................ 9 3.7 write ...................................................................................................................... 9 4.0 command definitions ........................................................................................ 9 4.1 read array command.........................................................................................13 4.2 read query mode command .............................................................................13 4.2.1 query structure output ..........................................................................13 4.2.2 query structure overview ......................................................................14 4.2.3 block status register .............................................................................15 4.2.4 cfi query identification string ...............................................................15 4.2.5 system interface information .................................................................16 4.2.6 device geometry definiction..................................................................17 4.2.7 primary-vendor specific extended query table....................................18 4.3 read identifier codes command ........................................................................19 4.4 read status register command.........................................................................20 4.5 clear status register command.........................................................................20 4.6 block erase command........................................................................................21 4.7 block erase suspend command ........................................................................21 4.8 write to buffer command....................................................................................22 4.9 byte/word program commands .........................................................................22 4.10 program suspend command..............................................................................23 4.11 set read configuration command .....................................................................23 4.11.1 read configuration ................................................................................23 4.12 configuration command .....................................................................................24 4.13 set block lock-bit commands............................................................................24 4.14 clear block lock-bits command.........................................................................24 4.15 protection register program command .............................................................25 4.15.1 reading the program protection register..............................................25 4.15.2 programming the program protection register .....................................25 4.15.3 locking the protection register .............................................................26
28f128j3a, 28F640J3A, 28f320j3a iv product preview 5.0 design considerations ................................................................................ 38 5.1 three-line output control .................................................................................. 38 5.2 sts and block erase, program, and lock-bit configuration polling .................. 38 5.3 power supply decoupling ................................................................................... 38 5.4 input signal transitions - reducing overshoots and undershoots when using buffers or transceivers ....................................................................................... 39 5.5 v cc , v pen , rp# transitions................................................................................ 39 5.6 power-up/down protection................................................................................. 39 5.7 power dissipation ............................................................................................... 40 6.0 electrical specifications ........................................................................ 41 6.1 absolute maximum ratings ................................................................................ 41 6.2 operating conditions .......................................................................................... 41 6.3 capacitance ........................................................................................................ 42 6.4 dc characteristics .............................................................................................. 42 6.5 ac characteristics read-only operations ...................................................... 45 6.6 ac characteristics write operations............................................................... 47 6.7 block erase, program, and lock-bit configuration performance ....................... 50 7.0 ordering information .................................................................................. 50 8.0 additional information ............................................................................... 51
product preview v 28f128j3a, 28F640J3A, 28f320j3a revision history date of revision version description 07/07/99 -001 original version

28f128j3a, 28F640J3A, 28f320j3a product preview 1 1.0 product overview the 0.25 3 volt intel strataflash memory family contains high-density memories organized as 16 mbytes or 8 mwords (128-mbit), 8 mbytes or 4 mwords (64-mbit), and 4 mbytes or 2 mwords (32-mbit). these devices can be accessed as 8- or 16-bit words. the 128-mbit device is organized as one-hundred-twenty-eight 128-kbyte (131,072 bytes) erase blocks. the 64-mbit device is organized as sixty-four 128-kbyte erase blocks while the 32-mbits device contains thirty-two 128- kbyte erase blocks. blocks are selectively and individually lockable and unlockable in-system. a 128-bit protection register has multiple uses, including unique flash device identification. the devices optimized architecture and interface dramatically increases read performance by supporting page-mode reads. this read mode is ideal for non-clock memory systems. a common flash interface (cfi) permits software algorithms to be used for entire families of devices. this allows device-independent, jedec id-independent, and forward- and backward- compatible software support for the specified flash device families. flash vendors can standardize their existing interfaces for long-term compatibility. scaleable command set (scs) allows a single, simple software driver in all host systems to work with all scs-compliant flash memory devices, independent of system-level packaging (e.g., memory card, simm, or direct-to-board placement). additionally, scs provides the highest system/device data transfer rates and minimizes device and system-level implementation costs. a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, program, and lock-bit configuration operations. a block erase operation erases one of the devices 128-kbyte blocks typically within one second independent of other blocks. each block can be independently erased 100,000 times. block erase suspend mode allows system software to suspend block erase to read or program data from any other block. similarly, program suspend allows system software to suspend programming (byte/ word program and write-to-buffer operations) to read data or execute code from any other block that is not being suspended. each device incorporates a write buffer of 32 bytes (16 words) to allow optimum programming performance. by using the write buffer, data is programmed in buffer increments. this feature can improve system program performance more than 20 times over non-write buffer writes. individual block locking uses block lock-bits to lock and unlock blocks. block lock-bits gate block erase and program operations. lock-bit configuration operations set and clear lock-bits (set block lock-bit and clear block lock-bits commands). the status register indicates when the wsms block erase, program, or lock-bit configuration operation is finished. the sts (status) output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status indication using sts minimizes both cpu overhead and system power consumption. when configured in level mode (default mode), it acts as a ry/ by# pin. when low, sts indicates that the wsm is performing a block erase, program, or lock-bit configuration. sts-high indicates that the wsm is ready for a new command, block erase is
28f128j3a, 28F640J3A, 28f320j3a 2 product preview suspended (and programming is inactive), program is suspended, or the device is in reset/power- down mode. additionally, the configuration command allows the sts pin to be configured to pulse on completion of programming and/or block erases. three ce pins are used to enable and disable the device. a unique ce logic design (see table 2, chip enable truth table ) reduces decoder logic typically required for multi-chip designs. external logic is not required when designing a single chip, a dual chip, or a 4-chip miniature card or simm module. the byte# pin allows either x8 or x16 read/writes to the device. byte# at logic low selects 8-bit mode; address a 0 selects between the low byte and high byte. byte# at logic high enables 16-bit operation; address a 1 becomes the lowest order address and address a 0 is not used (dont care). a device block diagram is shown in figure 1. when the device is disabled (see table 2, chip enable truth table ) and the rp# pin is at v cc , the standby mode is enabled. when the rp# pin is at gnd, a further power-down mode is enabled which minimizes power consumption and provides write protection during reset. a reset time (t phqv ) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (t phwl ) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. 3 volt intel strataflash memory devices are available in two package types. both 56-lead tsop (thin small outline package) and csp (chip scale package) support all offered densities. figures 2 and 3 show the pinouts. figure 1. 3 volt intel? strataflash? memory block diagram 32-mbit: thirty-two 64-mbit: sixty-four 128-mbit: one-hundred- twenty-eight 128-kbyte blocks input buffer output multiplexer y-gating program/erase voltage switch data comparator status register identifier register data register i/o logic address latch address counter x-decoder y-decoder input buffer output buffer gnd v cc v pen ce 0 ce 1 ce 2 we# oe# rp# byte# command user interface 32-mbit: a 0 - a 21 64-mbit: a 0 - a 22 128-mbit: a 0 - a 23 dq 0 - dq 15 v cc write buffer write state machine multiplexer query sts v ccq ce logic
28f128j3a, 28F640J3A, 28f320j3a product preview 3 table 1. lead descriptions symbol type name and function a 0 input byte-select address: selects between high and low byte when the device is in x8 mode. this address is latched during a x8 program cycle. not used in x16 mode (i.e., the a 0 input buffer is turned off when byte# is high). a 1C a 23 input address inputs: inputs for addresses during read and program operations. addresses are internally latched during a program cycle. 32-mbit: a 0C a 21 64-mbit: a 0C a 22 128-mbit: a 0C a 23 dq 0C dq 7 input/ output low-byte data bus: inputs data during buffer writes and programming, and inputs commands during command user interface (cui) writes. outputs array, query, identifier, or status data in the appropriate read mode. floated when the chip is de-selected or the outputs are disabled. outputs dq 6C dq 0 are also floated when the write state machine (wsm) is busy. check sr.7 (status register bit 7) to determine wsm status. dq 8C dq 15 input/ output high-byte data bus: inputs data during x16 buffer writes and programming operations. outputs array, query, or identifier data in the appropriate read mode; not used for status register reads. floated when the chip is de-selected, the outputs are disabled, or the wsm is busy. ce 0 , ce 1 , ce 2 input chip enables: activates the devices control logic, input buffers, decoders, and sense amplifiers. when the device is de-selected (see table 2, chip enable truth table ), power reduces to standby levels. all timing specifications are the same for these three signals. device selection occurs with the first edge of ce 0 , ce 1 , or ce 2 that enables the device. device deselection occurs with the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). rp# input reset/ power-down: resets internal automation and puts the device in power-down mode. rp#- high enables normal operation. exit from reset sets the device to read array mode. when driven low, rp# inhibits write operations which provides data protection during power transitions. oe# input output enable: activates the devices outputs through the data buffers during a read cycle. oe# is active low. we# input write enable: controls writes to the command user interface, the write buffer, and array blocks. we# is active low. addresses and data are latched on the rising edge of the we# pulse. sts open drain output status: indicates the status of the internal state machine. when configured in level mode (default mode), it acts as a ry/by# pin. when configured in one of its pulse modes, it can pulse to indicate program and/or erase completion. for alternate configurations of the status pin, see the configurations command. tie sts to v ccq with a pull-up resistor. byte# input byte enable: byte# low places the device in x8 mode. all data is then input or output on dq 0C dq 7 , while dq 8C dq 15 float. address a 0 selects between the high and low byte. byte# high places the device in x16 mode, and turns off the a 0 input buffer. address a 1 then becomes the lowest order address. v pen input erase / program / block lock enable: for erasing array blocks, programming data, or configuring lock-bits. with v pen v penlk , memory contents cannot be altered. v cc supply device power supply: with v cc v lko , all write attempts to the flash memory are inhibited. v ccq output buffer supply output buffer power supply: this voltage controls the devices output voltages. to obtain output voltages compatible with system data bus voltages, connect v ccq to the system supply voltage. gnd supply ground: do not float any ground pins. nc no connect: lead is not internally connected; it may be driven or floated.
28f128j3a, 28F640J3A, 28f320j3a 4 product preview 0667-02 notes: 1. address a 22 is only valid on 64-mbit densities and above, otherwise, it is a no connect (nc) 2. address a 23 is only valid on 128-mbit densities and above, otherwise, it is a no connect (nc) 3. address a 24 is only valid on 256-mbit densities and above, otherwise, it is a no connect (nc) 4. dont use (du) pins refer to pins that should not be connected figure 2. 3 volt intel? strataflash? memory easy bga package 1 2 3 4 5 6 7 8 a b c d e f g h top view - ball side down bottom view - ball side up a 1 a 6 a 8 v pen a 13 v cc a 18 a 22 (1) a 2 gnd a 9 ce 0 #a 14 du a 19 ce 1 # a 3 a 7 a 10 a 12 a 15 du a 20 a 21 a 4 a 5 a 11 dq 8 dq 1 dq 9 dq 3 dq 4 du dq 15 sts byte# dq 0 dq 10 dq 11 dq 12 du du oe# a 23 (2) a 0 dq 2 v ccq dq 5 dq 6 dq 14 we# ce 2 #du v cc gnd dq 13 gnd dq 7 a 24 (3) rp# du du a 16 a 17 8 7 6 5 4 3 2 1 a b c d e f g h a 22 (1) a 18 v cc a 13 v pen a 8 a 6 a 1 ce 1 #a 19 du a 14 ce 0 #a 9 gnd a 2 a 21 a 20 du a 15 a 12 a 10 a 7 a 3 a 17 a 16 du sts dq 15 du dq 4 dq 3 dq 9 dq 1 dq 8 oe# du du dq 12 dq 11 dq 10 dq 0 byte# we# dq 14 dq 6 dq 5 v ccq dq 2 a 0 a 23 (2) a 24 (3) dq 7 gnd dq 13 gnd v cc du ce 2 # du rp# a 11 a 5 a 4 32 mbit, 64 mbit and 128 mbit: 10 x 13 x 1.2 mm 1.0 mm-ball pitch
28f128j3a, 28F640J3A, 28f320j3a product preview 5 0667-03 notes: 1. a 22 exists on 64-, 128- and 256-mbit densities. on 32-mbit densities this pin is a no-connect (nc). 2. a 23 exists on 128-mbit densities. on 32- and 64-mbit densities this pin is a no-connect (nc). 3. a 24 exists on 256-mbit densities. on 32-, 64- and 128-mbit densities this pin is a no-connect (nc). 4. v cc = 5 v 10% for the 28f640j5/28f320j5. 2.0 principles of operation the intel strataflash memory devices include an on-chip wsm to manage block erase, program, and lock-bit configuration functions. it allows for 100% ttl-level control inputs, fixed power supplies during block erasure, program, lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from reset/power-down mode (see section 3.0, bus operations), the device defaults to read array mode. manipulation of external memory control pins allows array read, standby, and output disable operations. read array, status register, query, and identifier codes can be accessed through the cui (command user interface) independent of the v pen voltage. v penh on v pen enables successful block erasure, programming, and lock-bit configuration. all functions associated with altering memory contentsblock erase, program, lock-bit configurationare accessed via the cui and verified through the status register. figure 3. 3 volt intel? strataflash? memory 56-lead tsop (32/64/128 mbit) offers and easy migration from the 32-mbit intel strataflash component (28f320j5) or the 16-mbit flashfile? component (28f160s3) highlights pinout changes nc oe# sts we# dq 15 dq 14 dq 6 dq 7 gnd dq 5 dq 12 dq 13 dq 4 gnd dq 11 v ccq dq 3 dq 2 v cc (4) dq 10 dq 9 dq 8 dq 0 dq 1 a 0 nc ce 2 byte# 28f320j5 intel ? strataflash? memory 56-lead tsop standard pinout 14 mm x 20 mm top view 1 3 4 2 5 7 8 6 9 11 12 10 13 15 16 14 17 19 20 18 21 23 24 22 25 27 28 26 56 54 53 55 52 50 49 51 48 46 45 47 44 42 41 43 40 38 37 39 36 34 33 35 32 30 29 31 a 24 (3) oe# sts we# dq 15 dq 14 dq 6 dq 7 gnd dq 5 dq 12 dq 13 dq 4 gnd dq 11 v ccq dq 3 dq 2 v cc dq 10 dq 9 dq 8 dq 0 dq 1 a 0 ce 2 byte# a 21 a 20 ce 1 a 19 a 17 a 16 a 18 v cc a 14 a 13 a 15 a 12 v pen rp# ce 0 a 11 a 9 a 8 a 10 gnd a 6 a 5 a 7 a 4 a 2 a 1 a 3 a 22 (1) 3 volt intel strataflash memory 32/64/128m a 20 ce 1 a 19 a 17 a 16 a 18 v cc a 14 a 13 a 15 a 12 v pp rp# ce 0 a 11 a 9 a 8 a 10 gnd a 6 a 5 a 7 a 4 a 2 a 1 a 3 nc nc 28f160s3 a 23 (2) 3 volt intel strataflash memory 32/64/128m 28f320j5 nc a 21 a 20 ce 1 a 19 a 17 a 16 a 18 v cc (4) a 14 a 13 a 15 a 12 v pen rp# ce 0 a 11 a 9 a 8 a 10 gnd a 6 a 5 a 7 a 4 a 2 a 1 a 3 wp# oe# sts we# dq 15 dq 14 dq 6 dq 7 gnd dq 5 dq 12 dq 13 dq 4 gnd dq 11 v cc dq 3 dq 2 v cc dq 10 dq 9 dq 8 dq 0 dq 1 a 0 nc byte# nc 28f160s3
28f128j3a, 28F640J3A, 28f320j3a 6 product preview commands are written using standard micro-processor write timings. the cui contents serve as input to the wsm, which controls the block erase, program, and lock-bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification, and margining of data. addresses and data are internally latched during program cycles. interface software that initiates and polls progress of block erase, program, and lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read or program data from/to any other block. program suspend allows system software to suspend a program to read data from any other flash memory array location. 2.1 data protection depending on the application, the system designer may choose to make the v pen switchable (available only when memory block erases, programs, or lock-bit configurations are required) or hardwired to v penh . the device accommodates either design practice and encourages optimization of the processor-memory interface. when v pen v penlk , memory contents cannot be altered. the cuis two-step block erase, byte/word program, and lock-bit configuration command sequences provide protection from unwanted operations even when v penh is applied to v pen . all program functions are disabled when v cc is below the write lockout voltage v lko or when rp# is v il . the devices block locking capability provides additional protection from inadvertent code or data alteration by gating erase and program operations. 3.0 bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
28f128j3a, 28F640J3A, 28f320j3a product preview 7 notes: 1. for single-chip applications, ce 2 and ce 1 can be strapped to gnd. figure 4. memory map table 2. chip enable truth table (1) ce 2 ce 1 ce 0 device v il v il v il enabled v il v il v ih disabled v il v ih v il disabled v il v ih v ih disabled v ih v il v il enabled v ih v il v ih enabled v ih v ih v il enabled v ih v ih v ih disabled 64-kword block 64-kword block 64-kword block 64-kword block word wide (x16) mode 1fffff 1f0000 7fffff 7f0000 01ffff 010000 00ffff 000000 a [23-1]: 128 mbit a [22-1]: 64 mbit a [21-1]: 32 mbit 128-kbyte block 128-kbyte block 128-kbyte block 128-kbyte block byte-wide (x8) mode 3fffff 3e0000 ffffff fe0000 03ffff 020000 01ffff 000000 a [23-0]:128 mbit a [22-0]: 64 mbit a [21-0]: 32 mbit 32-mbit 64-mbit 64-kword block 3fffff 3f0000 128-kbyte block 7fffff 7e0000 31 1 0 127 63 31 1 0 127 63 128-mbit
28f128j3a, 28F640J3A, 28f320j3a 8 product preview 3.1 read information can be read from any block, query, identifier codes, or status register independent of the v pen voltage. upon initial device power-up or after exit from reset/power-down mode, the device automatically resets to read array mode. otherwise, write the appropriate read mode command (read array, read query, read identifier codes, or read status register) to the cui. six control pins dictate the data flow in and out of the component: ce 0 , ce 1 , ce 2 , oe#, we#, and rp#. the device must be enabled (see table 2, chip enable truth table ), and oe# must be driven active to obtain data at the outputs. ce 0 , ce 1 , and ce 2 are the device selection controls and, when enabled (see table 2, chip enable truth table ), select the memory device. oe# is the data output (dq 0C dq 15 ) control and, when active, drives the selected memory data onto the i/o bus. we# must be at v ih . when reading information in read array mode, the device supports two asynchronous read configurations: page-mode and standard byte/word reads. standard word/byte reading is the default read configuration state. page-mode reading is enabled by writing to the read configuration register. this mode provides high data transfer rate for memory subsystems. in this state, data is internally read and stored in a high-speed page buffer. a 2:0 addresses data in the page buffer. the page size is four words or eight bytes. 3.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins dq 0C dq 15 are placed in a high-impedance state. 3.3 standby ce 0 , ce 1 , and ce 2 can disable the device (see table 2, chip enable truth table ) and place it in standby mode which substantially reduces device power consumption. dq 0C dq 15 outputs are placed in a high-impedance state independent of oe#. if deselected during block erase, program, or lock- bit configuration, the wsm continues functioning, and consuming active power until the operation completes. 3.4 reset/power-down rp# at v il initiates the reset/power-down mode. in read modes, rp#-low deselects the memory, places output drivers in a high-impedance state, and turns off numerous internal circuits. rp# must be held low for a minimum of t plph . time t phqv is required after return from reset mode until initial memory access outputs are valid. after this wake- up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase, program, or lock-bit configuration modes, rp#-low will abort the operation. in default mode, sts transitions low and remains low for a maximum time of t plph + t phrh until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially corrupted after a program or partially altered after an erase or lock-bit configuration. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written.
28f128j3a, 28F640J3A, 28f320j3a product preview 9 as with any automated device, it is important to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, program, or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. intel ? flash memories allow proper initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu. 3.5 read query the read query operation outputs block status information, cfi (common flash interface) id string, system interface information, device geometry information, and intel-specific extended query information. 3.6 read identifier codes the read identifier codes operation outputs the manufacturer code, device code and the block lock configuration codes for each block (see figure 5). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block lock configuration codes identify locked and unlocked blocks. 3.7 write writing commands to the cui enables reading of device data, query, identifier codes, inspection and clearing of the status register, and, when v pen = v penh , block erasure, program, and lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the byte/word program command requires the command and address of the location to be written. set block lock-bit commands require the command and block within the device to be locked. the clear block lock-bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is written when the device is enabled and we# is active. the address and data needed to execute a command are latched on the rising edge of we# or the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). standard microprocessor write timings are used. 4.0 command definitions when the v pen voltage v penlk , only read operations from the status register, query, identifier codes, or blocks are enabled. placing v penh on v pen additionally enables block erase, program, and lock-bit configuration operations. device operations are selected by writing specific commands into the cui. table 4 defines these commands.
28f128j3a, 28F640J3A, 28f320j3a 10 product preview 0606-06a note: a 0 is not used in either x8 or x16 modes when obtaining these identifier codes. data is always given on the low byte in x16 mode (upper byte contains 00h). figure 5. device identifier code memory map reserved for future implementation (blocks 64 through 126) reserved for future implementation block 127 7fffff 7f0003 7f0002 7f0000 7effff word address a[23-1]: 128 mbit a[22-1]: 64 mbit a[21-1]: 32 mbit block 127 lock configuration reserved for future implementation reserved for future implementation (blocks 32 through 62) reserved for future implementation reserved for future implementation (blocks 2 through 30) reserved for future implementation reserved for future implementation block 63 block 31 block 1 block 0 lock configuration reserved for future implementation block 0 manufacturer code device code 3fffff 3f0003 3f0002 3f0000 3effff 1effff 1f0003 1f0002 1f0000 01ffff 010003 010002 010000 00ffff 000004 000003 000002 000001 000000 32 mbit 64 mbit block 31 lock configuration block 63 lock configuration block 1 lock configuration 128 mbit
28f128j3a, 28F640J3A, 28f320j3a product preview 11 notes: 1. refer to dc characteristics . when v pen v penlk , memory contents can be read, but not altered. 2. x can be v il or v ih for control and address pins, and v penlk or v penh for v pen . see dc characteristics for v penlk and v penh voltages. 3. in default mode, sts is v ol when the wsm is executing internal block erase, program, or lock-bit configuration algorithms. it is v oh when the wsm is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset/power-down mode. 4. see read identifier codes command section for read identifier code data. 5. see read query mode command section for read query data. 6. command writes involving block erase, program, or lock-bit configuration are reliably executed when v pen = v penh and v cc is within specification. 7. refer to table 4 for valid d in during a write operation. 8. dq refers to dq 0C dq 7 if byte# is low and dq 0C dq 15 if byte# is high. 9. high z will be v oh with an external pull-up resistor. 10.see table 2 for valid ce configurations. 11.oe# and we# should never be enabled simultaneously. table 3. bus operations mode notes rp# ce 0,1,2 (10) oe# (11) we# (11) address v pen dq (8) sts (default mode) read array 1,2,3 v ih enabled v il v ih xx d out high z (9) output disable v ih enabled v ih v ih x x high z x standby v ih disabled x x x x high z x reset/power-down mode v il x x x x x high z high z (9) read identifier codes v ih enabled v il v ih see figure 5 x note 4 high z (9) read query v ih enabled v il v ih see table 7 x note 5 high z (9) read status (wsm off) v ih enabled v il v ih xx d out read status (wsm on) v ih enabled v il v ih xv penh dq 7 = d out dq 15C8 = high z dq 6C0 = high z write 3,6,7 v ih enabled v ih v il xx d in x
28f128j3a, 28F640J3A, 28f320j3a 12 product preview notes: 1. bus operations are defined in table 3. 2. x = any valid address within the device. ba = address within the block. ia = identifier code address: see figure 5 and table 15. qa = query database address. pa = address of memory location to be programmed. rcd = data to be written to the read configuration register. this data is presented to the device on a 16-1 ; all other address inputs are ignored. 3. id = data read from identifier codes. qd = data read from query database. srd = data read from status register. see table 18 for a description of the status register bits. pd = data to be programmed at location pa. data is latched on the rising edge of we#. cc = configuration code. 4. the upper byte of the data bus (dq 8C dq 15 ) during command writes is a dont care in x16 operation. 5. following the read identifier codes command, read operations access manufacturer, device and block lock codes. see read identifier codes command section for read identifier code data. 6. if the wsm is running, only dq 7 is valid; dq 15C dq 8 and dq 6C dq 0 float, which places them in a high-impedance state. table 4. intel? strataflash? memory command set definitions (13) command scaleable or basic command set (14) bus cycles reqd. notes first bus cycle second bus cycle oper (1) addr (2) data (3,4) oper (1) addr (2) data (3,4) read array scs/bcs 1 write x ffh read identifier codes scs/bcs 3 2 5 write x 90h read ia id read query scs 3 2 write x 98h read qa qd read status register scs/bcs 2 6 write x 70h read x srd clear status register scs/bcs 1 write x 50h write to buffer scs/bcs > 2 7,8,9 write ba e8h write ba n word/byte program scs/bcs 2 10,11 write x 40h or 10h write pa pd block erase scs/bcs 2 9,10 write x 20h write ba d0h block erase, program suspend scs/bcs 1 10,15 write x b0h block erase, program resume scs/bcs 1 10 write x d0h configuration scs 2 write x b8h write x cc set read configuration 2 write x 60h write rcd 03h set block lock-bit scs 2 write x 60h write ba 01h clear block lock-bits scs 2 12 write x 60h write x d0h protection program 2 write x c0h write pa pd
28f128j3a, 28F640J3A, 28f320j3a product preview 13 7. after the write to buffer command is issued check the xsr to make sure a buffer is available for writing. 8. the number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. count ranges on this device for byte mode are n = 00h to n = 1fh and for word mode are n = 0000h to n = 000fh. the third and consecutive bus cycles, as determined by n, are for writing data into the write buffer. the confirm command (d0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence aborts the write to buffer operation. please see figure 7, write to buffer flowchart , for additional information. 9. the write to buffer or erase operation does not begin until a confirm command (d0h) is issued. 10.attempts to issue a block erase or program to a locked block while rp# is v ih will fail. 11.either 40h or 10h are recognized by the wsm as the byte/word program setup. 12.the clear block lock-bits operation simultaneously clears all block lock-bits. 13.commands other than those shown above are reserved by intel for future device implementations and should not be used. 14.the basic command set (bcs) is the same as the 28f008sa command set or intel standard command set. the scaleable command set (scs) is also referred to as the intel extended command set. 15.program suspends can be issued after either the write-to-buffer or word-/byte-program operation is initiated. 4.1 read array command upon initial device power-up and after exit from reset/power-down mode, the device defaults to read array mode. the read configuration register defaults to standard word/byte read mode. the read array command also causes the device to enter read array mode. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, program, or lock-bit configuration, the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase or program suspend command. the read array command functions independently of the v pen voltage. 4.2 read query mode command this section defines the data structure or database returned by the common flash interface (cfi) query command. system software should parse this structure to gain critical information such as block size, density, x8/x16, and electrical specifications. once this information has been obtained, the software will know which command sets to use to enable flash writes, block erases, and otherwise control the flash component. the query is part of an overall specification for multiple command set and control interface descriptions called common flash interface, or cfi. 4.2.1 query structure output the query database allows system software to gain information for controlling the flash component. this section describes the devices cfi-compliant interface that allows the host system to access query data. query data are always presented on the lowest-order data outputs (dq 0-7 ) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table device starting address is a 10h, which is a word address for x16 devices. for a word-wide (x16) device, the first two bytes of the query structure, q and r in ascii, appear on the low byte at word addresses 10h and 11h. this cfi-compliant device outputs 00h data on upper bytes. thus, the device outputs ascii q in the low byte (dq 0-7 ) and 00h in the high byte (dq 8-15 ).
28f128j3a, 28F640J3A, 28f320j3a 14 product preview at query addresses containing two or more bytes of information, the least significant data byte is presented at the lower address, and the most significant data byte is presented at the higher address. in all of the following tables, addresses and data are represented in hexadecimal notation, so the h suffix has been dropped. in addition, since the upper byte of word-wide devices is always 00h, the leading 00 has been dropped from the table notation and only the lower byte value is shown. any x16 device outputs can be assumed to have 00h on the upper byte in this mode. note: 1. the system must drive the lowest order addresses to access all the device's array data when the device is configured in x8 mode. therefore, word addressing, where these lower addresses are not toggled by the system, is "not applicable" for x8-configured devices. 4.2.2 query structure overview the query command causes the flash component to display the common flash interface (cfi) query structure or database. the structure sub-sections and address locations are summarized below. see ap-646 common flash interface (cfi) and command sets (order number 292204) for a full description of cfi. the following sections describe the query structure sub-sections in detail. table 5. summary of query structure output as a function of device and mode device type/ mode query start location in maximum device bus width addresses query data with maximum device bus width addressing query data with byte addressing hex offset hex code ascii value hex offset hex code ascii value x16 device 10h 10: 0051 q 20: 51 q x16 mode 11: 0052 r 21: 00 null 12: 0059 y 22: 52 r x16 device 20: 51 q x8 mode n/a (1) n/a (1 21: 51 q 22: 52 r table 6. example of query structure output of a x16- and x8-capable device word addressing byte addressing offset hex code value offset hex code value a 15C a 0 d 15C d 0 a 7C a 0 d 7C d 0 0010h 0051 q 20h 51 q 0011h 0052 r 21h 51 q 0012h 0059 y 22h 52 r 0013h p_id lo prvendor 23h 52 r 0014h p_id hi id # 24h 59 y 0015h p lo prvendor 25h 59 y 0016h p hi tbladr 26h p_id lo prvendor 0017h a_id lo altvendor 27h p_id lo id # 0018h a_id hi id # 28h p_id hi id # ... ... ... ... ... ...
28f128j3a, 28F640J3A, 28f320j3a product preview 15 notes: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 02000h is block 2s beginning location when the block size is 128 kbyte). 3. offset 15 defines p which points to the primary intel-specific extended query table. 4.2.3 block status register the block status register indicates whether an erase operation completed successfully or whether a given block is locked or can be accessed for flash program/erase operations. block erase status (bsr.1) allows system software to determine the success of the last block erase operation. bsr.1 can be used just after power-up to verify that the v cc supply was not accidentally removed during an erase operation. this bit is only reset by issuing another erase operation to the block. the block status register is accessed from word address 02h within each block. note: 1. ba = the beginning location of a block address (i.e., 008000h is block 1s (64-kb block) beginning location in word mode). 4.2.4 cfi query identification string the cfi query identification string provides verification that the component supports the common flash interface specification. it also indicates the specification version and supported vendor-specified command set(s). table 7. query structure offset sub-section name description 00h manufacturer code 01h device code (ba+2)h (2) block status register block-specific information 04-0fh reserved reserved for vendor-specific information 10h cfi query identification string reserved for vendor-specific information 1bh system interface information command set id and vendor data offset 27h device geometry definition flash device layout p (3) primary intel-specific extended query table vendor-defined additional information specific to the primary vendor algorithm table 8. block status register offset length description address value (ba+2)h (1) 1 block lock status register ba+2: --00 or --01 bsr.0 block lock status 0 = unlocked 1 = locked ba+2: (bit 0): 0 or 1 bsr.1 block erase status 0 = last erase operation completed successfully 1 = last erase operation did not complete successfully ba+2: (bit 1): 0 or 1 bsr 2C7: reserved for future use ba+2: (bit 2C7): 0
28f128j3a, 28F640J3A, 28f320j3a 16 product preview 4.2.5 system interface information the following device information can optimize system interface software. table 9. cfi identification offset length description add. hex code value 10h 3 query-unique ascii string qry 10 --51 q 11: --52 r 12: --59 y 13h 2 primary vendor command set and control interface id code. 13: --01 16-bit id code for vendor-specified algorithms 14: --00 15h 2 extended query table primary algorithm address 15: --31 16: --00 17h 2 alternate vendor command set and control interface id code. 17: --00 0000h means no second vendor-specified algorithm exists 18: --00 19h 2 secondary algorithm extended query table address. 19: --00 0000h means none exists 1a: --00 table 10. system interface information offset length description add. hex code value 1bh 1 v cc logic supply minimum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 bcd volts 1b: --27 2.7 v 1ch 1 v cc logic supply maximum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 bcd volts 1c: --36 3.6 v 1dh 1 v pp [programming] supply minimum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 hex volts 1d: --00 0.0 v 1eh 1 v pp [programming] supply maximum program/erase voltage bits 0C3 bcd 100 mv bits 4C7 hex volts 1e: --00 0.0 v 1fh 1 n such that typical single word program time-out = 2 n s 1f: --07 128 s 20h 1 n such that typical max. buffer write time-out = 2 n s 20: --07 128 s 21h 1 n such that typical block erase time-out = 2 n ms 21: --0a 1 s 22h 1 n such that typical full chip erase time-out = 2 n ms 22: --00 na 23h 1 n such that maximum word program time-out = 2 n times typical 23: --04 192 s 24h 1 n such that maximum buffer write time-out = 2 n times typical 24: --04 192 s 25h 1 n such that maximum block erase time-out = 2 n times typical 25: --04 16 s 26h 1 n such that maximum chip erase time-out = 2 n times typical 26: --00 na
28f128j3a, 28F640J3A, 28f320j3a product preview 17 4.2.6 device geometry definition this field provides critical details of the flash device geometry. device geometry definition table 11. device geometry definition offset length description code see table below 27h 1 n such that device size = 2 n in number of bytes 27: 28h 2 flash device interface: x8 async x16 async x8/x16 async 28: --02 x8/ x16 28:00,29:00 28:01,29:00 28:02,29:00 29: --00 2ah 2 n such that maximum number of bytes in write buffer = 2 n 2a: --05 32 2b: --00 2ch 1 number of erase block regions within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) x (individual block size) 2c: --01 1 2dh 4 erase block region 1 information 2d: bits 0C15 = y, y+1 = number of identical-size erase blocks 2e: bits 16C31 = z, region erase block(s) size are z x 256 bytes 2f: 30: address 32 mbit 64 mbit 128 mbit 27: --16 --17 --18 28: --02 --02 --02 29: --00 --00 --00 2a: --05 --05 --05 2b: --00 --00 --00 2c: --01 --01 --01 2d: --1f --3f --7f 2e: --00 --00 --00 2f: --00 --00 --00 30: --02 --02 --02
28f128j3a, 28F640J3A, 28f320j3a 18 product preview 4.2.7 primary-vendor specific extended query table certain flash features and commands are optional. the primary vendor-specific extended query table specifies this and other similar information. note: 1. future devices may not support the described legacy lock/unlock function. thus bit 3 would have a value of 0. table 12. primary vendor-specific extended query offset (1) p = 31h length description (optional flash features and commands) add. hex code value (p+0)h 3 primary extended query table 31: --50 p (p+1)h unique ascii string pri 32: --52 r (p+2)h 33: --49 i (p+3)h 1 major version number, ascii 34: --31 1 (p+4)h 1 minor version number, ascii 35: --31 1 (p+5)h (p+6)h (p+7)h (p+8)h 4 optional feature and command support (1=yes, 0=no) 36: --0a bits 9C31 are reserved; undefined bits are 0. if bit 31 is 37: --00 1 then another 31 bit field of optional features follows at 38: --00 the end of the bit-30 field. 39: --00 bit 0 chip erase supported bit 0 = 0 no bit 1 suspend erase supported bit 1 = 1 yes bit 2 suspend program supported bit 2 = 1 yes bit 3 legacy lock/unlock supported bit 3 = 1 (1) yes (1) bit 4 queued erase supported bit 4 = 0 no bit 5 instant individual block locking supported bit 5 = 0 no bit 6 protection bits supported bit 6 = 1 yes bit 7 page-mode read supported bit 7 = 1 yes bit 8 synchronous read supported bit 8 = 0 no (p+9)h 1 supported functions after suspend: read array, status, query other supported operations are: bits 1C7 reserved; undefined bits are 0 3a: --01 bit 0 program supported after erase suspend bit 0 = 1 yes (p+a)h (p+b)h 2 block status register mask 3b: --01 bits 2C15 are reserved; undefined bits are 0 3c: --00 bit 0 block lock-bit status register active bit 0 = 1 yes bit 1 block lock-down bit status active bit 1 = 0 no (p+c)h 1 v cc logic supply highest performance program/erase voltage bits 0C3 bcd value in 100 mv bits 4C7 bcd value in volts 3d: --33 3.3 v (p+d)h 1 v pp optimum program/erase supply voltage bits 0C3 bcd value in 100 mv bits 4C7 hex value in volts 3e: --00 0.0 v
28f128j3a, 28F640J3A, 28f320j3a product preview 19 note: 1. the variable p is a pointer which is defined at cfi offset 15h. note: 1. the variable p is a pointer which is defined at cfi offset 15h. 4.3 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in figure 5 retrieve the manufacturer, device and block lock configuration codes (see table 15 for identifier code values). page-mode reads are not supported in this read mode. to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v pen voltage. this command is valid only when the wsm is off or the device is suspended. following the read identifier codes command, the following information can be read: table 13. protection register information offset (1) p = 31h length description (optional flash features and commands) add. hex code value (p+e)h 1 number of protection register fields in jedec id space. 00h, indicates that 256 protection bytes are available 3f: --01 01 (p+f)h (p+10)h (p+11)h (p+12)h 4 protection field 1: protection description this field describes user-available one time programmable (otp) protection register bytes. some are pre-programmed with device-unique serial numbers. others are user- programmable. bits 0-15 point to the protection register lock byte, the sections first byte. the following bytes are factory pre-programmed and user-programmable. bits 0-7 = lock/bytes jedec-plane physical low address bits 8-15 = lock/bytes jedec-plane physical high address bits 16-23 = n such that 2 n = factory pre-programmed bytes bits 24-31 = n such that 2 n = user-programmable bytes 40: --00 00h table 14. burst read information offset (1) p = 31h length description (optional flash features and commands) add. hex code value (p+13)h 1 page mode read capability bits 0C7 = n such that 2 n hex value represents the number of read-page bytes. see offset 28h for device word width to determine page-mode data output width. 00h indicates no read page buffer. 44: --03 8 byte (p+14)h 1 number of synchronous mode read configuration fields that follow. 00h indicates no burst capability. 45: --00 0 (p+15)h reserved for future use 46:
28f128j3a, 28F640J3A, 28f320j3a 20 product preview notes: 1. a 0 is not used in either x8 or x16 modes when obtaining the identifier codes. the lowest order address line is a 1 . data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. x selects the specific blocks lock configuration code. see figure 5 for the device identifier code memory map. 4.4 read status register command the status register may be read to determine when a block erase, program, or lock-bit configuration is complete and whether the operation completed successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. page-mode reads are not supported in this read mode. the status register contents are latched on the falling edge of oe# or the first edge of ce 0 , ce 1 , or ce 2 that enables the device (see table 2, chip enable truth table ). oe# must toggle to v ih or the device must be disabled (see table 2, chip enable truth table ) before further reads to update the status register latch. the read status register command functions independently of the v pen voltage. during a program, block erase, set lock-bit, or clear lock-bit command sequence, only sr.7 is valid until the write state machine completes or suspends the operation. device i/o pins dq 0C dq 6 and dq 8C dq 15 are placed in a high-impedance state. when the operation completes or suspends (check status register bit 7), all contents of the status register are valid when read. 4.5 clear status register command status register bits sr.5, sr.4, sr.3, and sr.1 are set to 1s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 18). by allowing system software to reset these bits, several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v pen voltage. the clear status register command is only valid when the wsm is off or the device is suspended. table 15. identifier codes (1) code address(1) data manufacture code 00000 (00) 89 device code 32-mbit 00001 (00) 16 64-mbit 00001 (00) 17 128-mbit 00001 (00) 18 block lock configuration x 0002 (2) block is unlocked dq 0 = 0 block is locked dq 0 = 1 reserved for future use dq 1C7
28f128j3a, 28F640J3A, 28f320j3a product preview 21 4.6 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase confirm. this command sequence requires an appropriate address within the block to be erased (erase changes all block data to ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 10). the cpu can detect block erase completion by analyzing the output of the sts pin or status register bit sr.7. toggle oe#, ce 0 , ce 1 , or ce 2 to update the status register. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to 1. also, reliable block erasure can only occur when v cc is valid and v pen = v penh . if block erase is attempted while v pen v penlk , sr.3 and sr.5 will be set to 1. successful block erase requires that the corresponding block lock-bit be cleared. if block erase is attempted when the corresponding block lock-bit is set, sr.1 and sr.5 will be set to 1. 4.7 block erase suspend command the block erase suspend command allows block-erase interruption to read or program data in another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bit sr.7 then sr.6 can determine when the block erase operation has been suspended (both will be set to 1). in default mode, sts will also transition to v oh . specification t whrh defines the block erase suspend latency. at this point, a read array command can be written to read data from blocks other than that which is suspended. a program command sequence can also be issued during erase suspend to program data in other blocks. during a program operation with block erase suspended, status register bit sr.7 will return to 0 and sts output (in default mode) will transition to v ol . however, sr.6 will remain 1 to indicate block erase suspend status. using the program suspend command, a program operation can also be suspended. resuming a suspended programming operation by issuing the program resume command allows continuing of the suspended programming operation. to resume the suspended erase, the user must wait for the programming operation to complete before issuing the block erase resume command. the only other valid commands while block erase is suspended are read query, read status register, clear status register, configure, and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and sts (in default mode) will return to v ol . after the erase resume command is written, the device automatically outputs status register data when read (see figure 11). v pen must remain at v penh (the same v pen level used for block erase) while block erase is suspended. block erase cannot resume until program operations initiated during block erase suspend have completed.
28f128j3a, 28F640J3A, 28f320j3a 22 product preview 4.8 write to buffer command to program the flash device, a write to buffer command sequence is initiated. a variable number of bytes, up to the buffer size, can be loaded into the buffer and written to the flash device. first, the write to buffer setup command is issued along with the block address (see figure 7, write to buffer flowchart ). at this point, the extended status register (xsr, see table 19) information is loaded and xsr.7 reverts to "buffer available" status. if xsr.7 = 0, the write buffer is not available. to retry, continue monitoring xsr.7 by issuing the write to buffer setup command with the block address until xsr.7 = 1. when xsr.7 transitions to a 1, the buffer is ready for loading. now a word/byte count is given to the part with the block address. on the next write, a device start address is given along with the write buffer data. subsequent writes provide additional device addresses and data, depending on the count. all subsequent addresses must lie within the start address plus the count. internally, this device programs many flash cells in parallel. because of this parallel programming, maximum programming performance and lower power are obtained by aligning the start address at the beginning of a write buffer boundary (i.e., a 4C a 0 of the start address = 0). after the final buffer data is given, a write confirm command is issued. this initiates the wsm (write state machine) to begin copying the buffer data to the flash array. if a command other than write confirm is written to the device, an invalid command/sequence error will be generated and status register bits sr.5 and sr.4 will be set to a 1. for additional buffer writes, issue another write to buffer setup command and check xsr.7. if an error occurs while writing, the device will stop writing, and status register bit sr.4 will be set to a 1 to indicate a program failure. the internal wsm verify only detects errors for 1s that do not successfully program to 0s. if a program error is detected, the status register should be cleared. any time sr.4 and/or sr.5 is set (e.g., a media failure occurs during a program or an erase), the device will not accept any more write to buffer commands. additionally, if the user attempts to program past an erase block boundary with a write to buffer command, the device will abort the write to buffer operation. this will generate an "invalid command/sequence" error and status register bits sr.5 and sr.4 will be set to a 1. reliable buffered writes can only occur when v pen = v penh . if a buffered write is attempted while v pen v penlk , status register bits sr.4 and sr.3 will be set to 1. buffered write attempts with invalid v cc and v pen voltages produce spurious results and should not be attempted. finally, successful programming requires that the corresponding block lock-bit be reset. if a buffered write is attempted when the corresponding block lock-bit is set, sr.1 and sr.4 will be set to 1. 4.9 byte/word program commands byte/word program is executed by a two-cycle command sequence. byte/word program setup (standard 40h or alternate 10h) is written followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the program and program verify algorithms internally. after the program sequence is written, the device automatically outputs status register data when read (see figure 8). the cpu can detect the completion of the program event by analyzing the sts pin or status register bit sr.7.
28f128j3a, 28F640J3A, 28f320j3a product preview 23 when program is complete, status register bit sr.4 should be checked. if a program error is detected, the status register should be cleared. the internal wsm verify only detects errors for 1s that do not successfully program to 0s. the cui remains in read status register mode until it receives another command. reliable byte/word programs can only occur when v cc and v pen are valid. if a byte/word program is attempted while v pen v penlk , status register bits sr.4 and sr.3 will be set to 1. successful byte/ word programs require that the corresponding block lock-bit be cleared. if a byte/word program is attempted when the corresponding block lock-bit is set, sr.1 and sr.4 will be set to 1. 4.10 program suspend command the program suspend command allows program interruption to read data in other flash memory locations. once the programming process starts (either by initiating a write to buffer or byte/word program operation), writing the program suspend command requests that the wsm suspend the program sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the program suspend command is written. polling status register bits sr.7 can determine when the programming operation has been suspended. when sr.7 = 1, sr.2 should also be set to 1, indicating that the device is in the program suspend mode. sts in level ry/by# mode will also transition to v oh . specification t whrh1 defines the program suspend latency. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while programming is suspended are read query, read status register, clear status register, configure, and program resume. after a program resume command is written, the wsm will continue the programming process. status register bits sr.2 and sr.7 will automatically clear and sts in ry/by# mode will return to v ol . after the program resume command is written, the device automatically outputs status register data when read. v pen must remain at v penh and v cc must remain at valid v cc levels (the same v pen and v cc levels used for programming) while in program suspend mode. refer to figure 9 for the program suspend/resume flowchart . 4.11 set read configuration command the set read configuration command writes data to the read configuration register. this operation is initiated by a two-cycle command sequence. read configuration setup is written, followed by a second write that specifies the data to be written to the read configuration register. this data is placed on the address bus, a 16:1 , and is latched on the rising edge of ce x or we# (whichever occurs first). the read configuration data sets the devices read configuration to either page-mode or standard word/byte reads. the command functions independently of the applied v pen voltage. after executing this command, the device returns to read array mode. 4.11.1 read configuration the device supports two asynchronous read configurations: standard word/byte reads or page- mode reads. bit rcr.16 in the read configuration register sets the read configuration. standard word/byte reading is the default read configuration state. parameter blocks, status register, and identifier only support standard word/byte single read operations.
28f128j3a, 28F640J3A, 28f320j3a 24 product preview 4.12 configuration command the status (sts) pin can be configured to different states using the configuration command. once the sts pin has been configured, it remains in that configuration until another configuration command is issued or rp# is asserted low. initially, the sts pin defaults to ry/by# operation where ry/by# low indicates that the state machine is busy. ry/by# high indicates that the state machine is ready for a new operation or suspended. table 17 displays the possible sts configurations. to reconfigure the status (sts) pin to other modes, the configuration command is given followed by the desired configuration code. the three alternate configurations are all pulse mode for use as a system interrupt as described below. for these configurations, bit 0 controls erase complete interrupt pulse, and bit 1 controls program complete interrupt pulse. supplying the 00h configuration code with the configuration command resets the sts pin to the default ry/by# level mode. the possible configurations and their usage are described in table 17. the configuration command may only be given when the device is not busy or suspended. check sr.7 for device status. an invalid configuration code will result in both status register bits sr.4 and sr.5 being set to 1. when configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250 ns. 4.13 set block lock-bit commands a flexible block locking and unlocking scheme is enabled via block lock-bits. the block lock-bits gate program and erase operations. individual block lock-bits can be set using the set block lock- bit command. this command is invalid while the wsm is running or the device is suspended. set block lock-bit commands are executed by a two-cycle sequence. the set block setup along with appropriate block address is followed by either the set block lock-bit confirm (and an address within the block to be locked). the wsm then controls the set lock-bit algorithm. after the sequence is written, the device automatically outputs status register data when read (see figure 12). the cpu can detect the completion of the set lock-bit event by analyzing the sts pin output or status register bit sr.7. when the set lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. an invalid set block lock-bit command will result in status register bits sr.4 and sr.5 being set to 1. also, reliable operations occur only when v cc and v pen are valid. with v pen v penlk , lock-bit contents are protected against alteration. 4.14 clear block lock-bits command all set block lock-bits are cleared in parallel via the clear block lock-bits command. block lock- bits can be cleared using only the clear block lock-bits command. this command is invalid while the wsm is running or the device is suspended.
28f128j3a, 28F640J3A, 28f320j3a product preview 25 clear block lock-bits command is executed by a two-cycle sequence. a clear block lock-bits setup is first written. the device automatically outputs status register data when read (see figure 13). the cpu can detect completion of the clear block lock-bits event by analyzing the sts pin output or status register bit sr.7. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bit error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. an invalid clear block lock-bits command sequence will result in status register bits sr.4 and sr.5 being set to 1. also, a reliable clear block lock-bits operation can only occur when v cc and v pen are valid. if a clear block lock-bits operation is attempted while v pen v penlk , sr.3 and sr.5 will be set to 1. if a clear block lock-bits operation is aborted due to v pen or v cc transitioning out of valid range, block lock-bit values are left in an undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. 4.15 protection register program command the 3 volt intel strataflash memory includes a 128-bit protection register that can be used to increase the security of a system design. for example, the number contained in the protection register can be used to mate the flash component with other system components such as the cpu or asic, preventing device substitution. the 128-bits of the protection register are divided into two 64-bit segments. one of the segments is programmed at the intel factory with a unique 64-bit number, which is unchangeable. the other segment is left blank for customer designers to program as desired. once the customer segment is programmed, it can be locked to prevent reprogramming. 4.15.1 reading the protection register the protection register is read in the identification read mode. the device is switched to this mode by writing the read identifier command (90h). once in this mode, read cycles from addresses shown in table 20 or table 21 retrieve the specified information. to return to read array mode, write the read array command (ffh). 4.15.2 programming the protection register the protection register bits are programmed using the two-cycle protection program command. the 64-bit number is programmed 16 bits at a time for word-wide parts and eight bits at a time for byte-wide parts. first write the protection program setup command, c0h. the next write to the device will latch in address and data and program the specified location. the allowable addresses are shown in table 20 or table 21. see figure 14 for the protection register programming flowchart . any attempt to address protection program commands outside the defined protection register address space will result in a status register error (program error bit sr.4 will be set to 1). attempting to program a locked protection register segment will result in a status register error (program error bit sr.4 and lock error bit sr.1 will be set to 1).
28f128j3a, 28F640J3A, 28f320j3a 26 product preview 4.15.3 locking the protection register the user-programmable segment of the protection register is lockable by programming bit 1 of the pr-lock location to 0. bit 0 of this location is programmed to 0 at the intel factory to protect the unique device number. bit 1 is set using the protection program command to program fffd to the pr-lock location. after these bits have been programmed, no further changes can be made to the values stored in the protection register. protection program commands to a locked section will result in a status register error (program error bit sr.4 and lock error bit sr.1 will be set to 1). protection register lockout state is not reversible. otp_map note: a 0 is not used in x16 mode when accessing the protection register map (see table 20 for x16 addressing). for x8 mode a 0 is used (see table 21 for x8 addressing). figure 6. protection register memory map 4 words factory programmed 4 words user programmed 1 word lock 88h 85h 84h 81h 80h word address a[23 - 1]: 128 mbit a[22 - 1]: 64 mbit a[21 - 1]: 32 mbit table 16. read configuration register definition rm r r r r r r r 16 (a 16 )15 14 13121110 9 rrrrrrrr 87654321 notes: rcr.16 = read mode (rm) 0 = standard word/byte reads enabled (default) 1 = page-mode reads enabled read mode configuration effects reads from the flash array. status register, query, and identifier reads support standard word/byte read cycles. rcr.15C1 = reserved for future enhancements (r) these bits are reserved for future use. set these bits to 0.
28f128j3a, 28F640J3A, 28f320j3a product preview 27 note: when the device is configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250 ns. table 17. configuration coding definitions reserved pulse on program complete (1) pulse on erase compete (1) bits 72 bit 1 bit 0 dq 7C dq 2 = reserved dq 1C dq 0 = sts pin configuration codes 00 = default, level mode ry/by# (device ready) indication 01 = pulse on erase complete 10 = pulse on program complete 11 = pulse on erase or program complete configuration codes 01b, 10b, and 11b are all pulse mode such that the sts pin pulses low then high when the operation indicated by the given configuration is completed. configuration command sequences for sts pin configuration (masking bits dq 7C dq 2 to 00h) are as follows: default ry/by# level mode: b8h, 00h er int (erase interrupt): b8h, 01h pulse-on-erase complete pr int (program interrupt): b8h, 02h pulse-on-program complete er/pr int (erase or program interrupt): b8h, 03h pulse-on-erase or program complete dq 7C dq 2 are reserved for future use. default (dq 1C dq 0 = 00) ry/by#, level mode used to control hold to a memory controller to prevent accessing a flash memory subsystem while any flash device's wsm is busy. configuration 01 er int, pulse mode used to generate a system interrupt pulse when any flash device in an array has completed a block erase or sequence of queued block erases. helpful for reformatting blocks after file system free space reclamation or cleanup configuration 10 pr int, pulse mode used to generate a system interrupt pulse when any flash device in an array has complete a program operation. provides highest performance for servicing continuous buffer write operations. configuration 11 er/pr int, pulse mode used to generate system interrupts to trigger servicing of flash arrays when either erase or program operations are completed when a common interrupt service routine is desired.
28f128j3a, 28F640J3A, 28f320j3a 28 product preview table 18. status register definitions wsms ess eclbs pslbs vpens r dps r bit 7 bit 6 bit 5 bit 4 bit 3 bit2 bit 1 bit 0 high z when busy? status register bits notes no yes yes yes yes yes yes yes sr.7 = write state machine status 1 = ready 0 = busy sr.6 = erase suspend status 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear lock-bits status 1 = error in block erasure or clear lock-bits 0 = successful block erase or clear lock-bits sr.4 = program and set lock-bit status 1 = error in setting lock-bit 0 = successful set block lock bit sr.3 = programming voltage status 1 = low programming voltage detected, operation aborted 0 = programming voltage ok sr.2 = program suspend status 1 = program suspended 0 = program in progress/completed sr.1 = device protect status 1 = block lock-bit detected, operation abort 0 = unlock sr.0 = reserved for future enhancements check sts or sr.7 to determine block erase, program, or lock-bit configuration completion. sr.6C sr.0 are not driven while sr.7 = 0. if both sr.5 and sr.4 are 1s after a block erase or lock-bit configuration attempt, an improper command sequence was entered. sr.3 does not provide a continuous programming voltage level indication. the wsm interrogates and indicates the programming voltage level only after block erase, program, set block lock-bit, or clear block lock-bits command sequences. sr.1 does not provide a continuous indication of block lock-bit values. the wsm interrogates the block lock-bits only after block erase, program, or lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set. read the block lock configuration codes using the read identifier codes command to determine block lock-bit status. sr.0 is reserved for future use and should be masked when polling the status register. table 19. extended status register definitions wbs reserved bit 7 bits 60 high z when busy? status register bits notes no yes xsr.7 = write buffer status 1 = write buffer available 0 = write buffer not available xsr.6Cxsr.0 = reserved for future enhancements after a buffer-write command, xsr.7 = 1 indicates that a write buffer is available. sr.6Csr.0 are reserved for future use and should be masked when polling the status register.
28f128j3a, 28F640J3A, 28f320j3a product preview 29 note: 1. all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a 23C a 9 = 0. note: 1. all address lines not specified in the above table must be 0 when accessing the protection register, i.e., a 23C a 9 = 0. table 20. word-wide protection register addressing word use a8 a7 a6 a5 a4 a3 a2 a1 lockboth10000000 0factory10000001 1factory10000010 2factory10000011 3factory10000100 4user10000101 5user10000110 6user10000111 7user10001000 table 21. byte-wide protection register addressing byte use a8 a7 a6 a5 a4 a3 a2 a1 lockboth10000000 lockboth10000000 0factory10000001 1factory10000001 2factory10000010 3factory10000010 4factory10000011 5factory10000011 6factory10000100 7factory10000100 8user10000101 9user10000101 auser10000110 buser10000110 cuser10000111 duser10000111 euser10001000 fuser10001000
28f128j3a, 28F640J3A, 28f320j3a 30 product preview 0606_07a figure 7. write to buffer flowchart start write word or byte count, block address write buffer data, start address x = 0 x = x + 1 write next buffer data, device address abort write to buffer command? check x = n? another write to buffer? read status register sr.7 = programming complete read extended status register xsr.7 = 1 no yes no no 1 write to buffer aborted yes no yes full status check if desired program buffer to flash confirm d0h issue write to buffer command e8h, block address write to another block address write to buffer time-out? 0 set time-out issue read status command yes bus operation command comments write write to buffer data = e8h block address read xsr. 7 = valid addr = block address standby check xsr. 7 1 = write buffer available 0 = write buffer not available write (note 1, 2) data = n = word/byte count n = 0 corresponds to count = 1 addr = block address write (note 3, 4) data = write buffer data addr = device start address write (note 5, 6) data = write buffer data addr = device address write program buffer to flash confirm data = d0h addr = block address read (note 7) status register data with the device enabled, oe# low updates sr addr = block address standby check sr.7 1 = wsm ready 0 = wsm busy 1. byte or word count values on dq 0 - dq 7 are loaded into the count register. count ranges on this device for byte mode are n = 00h to 1fh and for word mode are n = 0000h to 000fh. 2. the device now outputs the status register when read (xsr is no longer available). 3. write buffer contents will be programmed at the device start address or destination flash address. 4. align the start address on a write buffer boundary for maximum programming performance (i.e., a 4 - a 0 of the start address = 0). 5. the device aborts the write to buffer command if the current address is outside of the original block address. 6. the status register indicates an "improper command sequence" if the write to buffer command is aborted. follow this with a clear status register command. 7. toggling oe# (low to high to low) updates the status register. this can be done in place of issuing the read status register command. full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. 0 1
28f128j3a, 28F640J3A, 28f320j3a product preview 31 figure 8. byte/word program flowchart start write 40h, address write data and address read status register sr.7 = full status check if desired byte/word program complete read status register data (see above) voltage range error device protect error programming error byte/word program successful sr.3 = sr.1 = sr.4 = full status check procedure bus operation write write standby 1. toggling oe# (low to high to low) updates the status register. this can be done in place of issuing the read status register command. repeat for subsequent programming operations. sr full status check can be done after each program operation, or after a sequence of programming operations. write ffh after the last program operation to place device in read array mode. bus operation standby standby toggling oe# (low to high to low) updates the status register. this can be done in place of issuing the read status register command. repeat for subsequent programming operations. sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. 0 1 1 0 1 0 1 0 command setup byte/ word program byte/word program comments data = 40h addr = location to be programmed data = data to be programmed addr = location to be programmed check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = programming to voltage error detect check sr.4 1 = programming error read (note 1) status register data standby check sr.1 1 = device protect detect rp# = v ih , block lock-bit is set only required for systems implemeting lock-bit configuration.
28f128j3a, 28F640J3A, 28f320j3a 32 product preview 0606_085 figure 9. program suspend/resume flowchart start write b0h read status register sr.7 = sr.2 = programming completed write d0h programming resumed write ffh read array data 1 1 0 0 bus operation command comments write program suspend data = b0h addr = x read status register data addr = x standby check sr.7 1 - wsm ready 0 = wsm busy standby check sr.6 1 = programming suspended 0 = programming completed read read array locations other than that being programmed. write ffh read data array done reading yes no write read array data = ffh addr = x write program resume data = d0h addr = x
28f128j3a, 28F640J3A, 28f320j3a product preview 33 0606_09 figure 10. block erase flowchart erase block time-out? start read status register sr.7 = erase flash block(s) complete 0 1 no full status check if desired suspend erase no device supports queuing issue block queue erase command 28h, block address read extended status register is queue available? xsr.7= another block erase? issue erase command 28h block address read extended status register write confirm d0h block address another block erase? is queue full? xsr.7= 0=yes 1=no yes no 1=yes yes issue single block erase command 20h, block address no 0=no no suspend erase loop yes yes write confirm d0h block address set time-out issue read status command queued erase section (include this section for compatibility with future scs-compliant devices) bus operation command comments write erase block data = 28h or 20h addr = block address read xsr.7 = valid addr = x standby check xsr.7 1 = erase queue avail. 0 = no erase queue avail. write erase block data = 28h addr = block address read sr.7 = valid; sr.6 - 0 = x with the device enabled, oe# low updates sr addr = x standby check xsr.7 1 = erase queue avail. 0 = no erase queue avail. write (note 1) erase confirm data = d0h addr = x read status register data with the device enabled, oe# low updates sr addr = x standby check sr.7 1 = wsm ready 0 = wsm busy 1. the erase confirm byte must follow erase setup when the erase queue status (xsr.7) = 0. full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. yes
28f128j3a, 28F640J3A, 28f320j3a 34 product preview 0606_10 figure 11. block erase suspend/resume flowchart start write b0h read status register sr.7 = sr.6 = block erase completed read or program? done? write d0h block erase resumed write ffh read array data program program loop read array data read no yes 1 1 0 0 bus operation command comments write erase suspend data = b0h addr = x read status register data addr = x standby check sr.7 1 - wsm ready 0 = wsm busy standby check sr.6 1 = block erase suspended 0 = block erase completed write erase resume data = d0h addr = x
28f128j3a, 28F640J3A, 28f320j3a product preview 35 0606_11b figure 12. set block lock-bit flowchart start write 60h, block address write 01h/f1h, block address read status register sr.7 = full status check if desired set lock-bit complete full status check procedure bus operation write write standby repeat for subsequent lock-bit operations. full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations write ffh after the last lock-bit set operation to place device in read array mode. bus operation standby sr.5, sr.4, and sr.3 are only cleared by the clear status register command, in cases where multiple lock-bits are set before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. 1 0 command set block lock-bit setup set block lock-bit confirm comments data = 60h addr =block address data = 01h addr = block address check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = programming voltage error detect read status register data (see above) voltage range error sr.3 = 1 0 command sequence error sr.4,5 = 1 0 set lock-bit error sr.4 = 1 0 read status register data standby check sr.4, 5 both 1 = command sequence error standby check sr.4 1 = set lock-bit error set lock-bit successful
28f128j3a, 28F640J3A, 28f320j3a 36 product preview 0606_12b figure 13. clear lock-bit flowchart start write 60h write d0h read status register sr.7 = full status check if desired clear block lock-bits complete full status check procedure bus operation write write standby write ffh after the clear lock-bits operation to place device in read array mode. bus operation standby sr.5, sr.4, and sr.3 are only cleared by the clear status register command. if an error is detected, clear the status register before attempting retry or other error recovery. 1 0 command clear block lock-bits setup clear block or lock-bits confirm comments data = 60h addr = x data = d0h addr = x check sr.7 1 = wsm ready 0 = wsm busy command comments check sr.3 1 = programming voltage error detect read status register data (see above) voltage range error sr.3 = 1 0 command sequence error sr.4,5 = 1 0 clear block lock-bits error sr.5 = 1 0 read status register data standby check sr.4, 5 both 1 = command sequence error standby check sr.5 1 = clear block lock-bits error clear block lock-bits successful
28f128j3a, 28F640J3A, 28f320j3a product preview 37 figure 14. protection register programming flowchart start write c0h (protection reg. program setup) write protect. register address/data read status register sr.7 = 1? full status check if desired program complete read status register data (see above) v pen range error protection register programming error attempted program to locked register - aborted program successful sr.3, sr.4 = sr.1, sr.4 = sr.1, sr.4 = full status check procedure bus operation write write standby protection program operations can only be addressed within the protection register address space. addresses outside the defined space will return an error. repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus operation standby standby sr.3 must be cleared, if set during a program attempt, before further attempts are allowed by the write state machine. sr.1, sr.3 and sr.4 are only cleared by the clear staus register command, in cases of multiple protection register program operations before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery. no yes 1, 1 0,1 1,1 command protection program setup protection program comments data = c0h data = data to program addr = location to program check sr.7 1 = wsm ready 0 = wsm busy command comments sr.1 sr.3 sr.4 0 1 1 v pen low 0 0 1 prot. reg. prog. error 1 0 1 register locked: aborted read status register data toggle ce# or oe# to update status register data standby
28f128j3a, 28F640J3A, 28f320j3a 38 product preview 5.0 design considerations 5.1 three-line output control the device will often be used in large memory arrays. intel provides five control inputs (ce 0 , ce 1 , ce 2 , oe#, and rp#) to accommodate multiple memory connections. this control provides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable the device (see table 2, chip enable truth table ) while oe# should be connected to all memory devices and the systems read# control line. this assures that only selected memory devices have active outputs while de- selected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 sts and block erase, program, and lock-bit configuration polling sts is an open drain output that should be connected to v ccq by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock-bit configuration completion. in default mode, it transitions low after block erase, program, or lock-bit configuration commands and returns to high z when the wsm has finished executing the internal algorithm. for alternate configurations of the sts pin, see the configuration command. sts can be connected to an interrupt input of the system cpu or controller. it is active at all times. sts, in default mode, is also high z when the device is in block erase suspend (with programming inactive), program suspend, or in reset/power-down mode. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of ce 0 , ce 1 , ce 2 , and oe#. transient current magnitudes depend on the device outputs capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. since intel strataflash memory devices draw their power from three v cc pins (these devices do not include a v pp pin), it is recommended that systems without separate power and ground planes attach a 0.1 f ceramic capacitor between each of the devices three v cc pins (this includes v ccq ) and ground. these high- frequency, low-inductance capacitors should be placed as close as possible to package leads on each intel strataflash memory device. each device should have a 0.1 f ceramic capacitor connected between its v cc and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7 f electrolytic capacitor should be placed between v cc and gnd at the arrays power supply connection. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance.
28f128j3a, 28F640J3A, 28f320j3a product preview 39 5.4 input signal transitions - reducing overshoots and undershoots when using buffers or transceivers as faster, high-drive devices such as transceivers or buffers drive input signals to flash memory devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory specifications (see section 6.1, absolute maximum ratings ). many buffer/transceiver vendors now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs. internal output-damping resistors diminish the nominal output drive currents, while still leaving sufficient drive capability for most applications. these internal output-damping resistors help reduce unnecessary overshoots and undershoots. transceivers or buffers with balanced- or light- drive outputs also reduce overshoots and undershoots by diminishing output-drive currents. when considering a buffer/transceiver interface design to flash, devices with internal output-damping resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. for additional information, please refer to the ap-647 5 volt intel strataflash? memory design guide . 5.5 v cc , v pen , rp# transitions block erase, program, and lock-bit configuration are not guaranteed if v pen or v cc falls outside of the specified operating ranges, or rp# 1 v ih . if rp# transitions to v il during block erase, program, or lock-bit configuration, sts (in default mode) will remain low for a maximum time of t plph + t phrh until the reset operation is complete. then, the operation will abort and the device will enter reset/ power-down mode. the aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock-bit configuration. therefore, block erase and lock-bit configuration commands must be repeated after normal operation is restored. device power-off or rp# = v il clears the status register. the cui latches commands issued by system software and is not altered by v pen , ce 0 , ce 1 , or ce 2 transitions, or wsm actions. its state is read array mode upon power-up, after exit from reset/ power-down mode, or after v cc transitions below v lko . v cc must be kept at or above v pen during v cc transitions. after block erase, program, or lock-bit configuration, even after v pen transitions down to v penlk , the cui must be placed in read array mode via the read array command if subsequent access to the memory array is desired. v pen must be kept at or below v cc during v pen transitions. 5.6 power-up/down protection the device is designed to offer protection against accidental block erasure, programming, or lock- bit configuration during power transitions. internal circuitry resets the cui to read array mode at power-up. a system designer must guard against spurious writes for v cc voltages above v lko when v pen is active. since we# must be low and the device enabled (see table 2, chip enable truth table ) for a command write, driving we# to v ih or disabling the device will inhibit writes. the cuis two-step command sequence architecture provides added protection against data alteration. keeping v pen below v penlk prevents inadvertent data alteration. in-system block lock and unlock capability protects the device against inadvertent programming. the device is disabled while rp# = v il regardless of its control inputs.
28f128j3a, 28F640J3A, 28f320j3a 40 product preview 5.7 power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memorys nonvolatility increases usable battery life because data is retained when system power is removed.
28f128j3a, 28F640J3A, 28f320j3a product preview 41 6.0 electrical specifications 6.1 absolute maximum ratings notes: 1. all specified voltages are with respect to gnd. minimum dc voltage is C0.5 v on input/output pins and C0.2 v on v cc and v pen pins. during transitions, this level may undershoot to C2.0 v for periods <20 ns. maximum dc voltage on input/output pins, v cc , and v pen is v cc +0.5 v which, during transitions, may overshoot to v cc +2.0 v for periods <20 ns. 2. maximum dc voltage on rp# may overshoot to +14.0 v for periods <20 ns. 3. rp# voltage is normally at v il or v ih . connection to supply of v hh is allowed for a maximum cumulative period of 80 hours. 4. output shorted for no more than one second. no more than one output shorted at a time. warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. 6.2 operating conditions parameter maximum rating temperature under bias expanded C20 c to +70 c storage temperature C65 c to +125 c voltage on any pin (except rp#) C2.0 v to +5.0 v (1) rp# voltage with respect to gnd during lock-bit configuration operations C2.0 v to +14.0 v (1,2,3) output short circuit current 100 ma (4) notice: this datasheet contains information on products in the design phase of development. do not finalize a design with this information. revised information will be published when the product becomes available. verify with your local intel sales office that you have the latest datasheet before finalizing a design . table 22. temperature and v cc operating conditions symbol parameter notes min max unit test condition t a operating temperature C20 +70 c ambient temperature v cc1 v cc1 supply voltage (2.7 v - 3.6 v) 2.70 3.60 v v cc2 v cc2 supply voltage (3.0 v - 3.6 v) 3.00 3.60 v v ccq1 v ccq1 supply voltage (5 v 10%) 4.50 5.50 v v ccq2 v ccq2 supply voltage (2.7 v - 3.6 v) 2.70 3.60 v v ccq3 v ccq3 supply voltage (3.0 v - 3.6 v) 3.00 3.60 v
28f128j3a, 28F640J3A, 28f320j3a 42 product preview 6.3 capacitance (1) t a = +25 c, f = 1 mhz notes: 1. sampled, not 100% tested. 6.4 dc characteristics symbol parameter typ max unit condition c in input capacitance 6 8 pf v in = 0.0 v c out output capacitance 8 12 pf v out = 0.0 v symbol parameter notes typ max unit test conditions i li input and v pen load current 1 1 m a v cc = v cc max; v ccq = v ccq max v in = v ccq or gnd i lo output leakage current 1 10 m a v cc = v cc max; v ccq = v ccq max v in = v ccq or gnd i lo output leakage current 1 10 m a v cc = v cc max; v ccq = v ccq max v in = v ccq or gnd i ccs v cc standby current 1,3,5,9 50 100 m a cmos inputs, v cc = v cc max, device is enabled (see table 2, chip enable truth table ), rp# = v ccq 0.2 v 0.71 2 ma ttl inputs, v cc = v cc max, device is enabled (see table 2, chip enable truth table ), rp# = v ih i ccd v cc power-down current 9 50 100 m a rp# = gnd 0.2 v, i out (sts) = 0 ma i ccr v cc read current 1,5,9 35 55 ma cmos inputs, v cc = v cc max, v ccq = v ccq max using standard word/byte single reads device is enabled (see table 2, chip enable truth table ) f = 5 mhz, i out = 0 ma 45 65 ma ttl inputs,v cc = v cc max, v ccq = v ccq max using standard word/byte single reads device is enabled (see table 2, chip enable truth table ) f = 5 mhz, i out = 0 ma i ccr v cc read current 1,5,9 tbd tbd ma cmos inputs, v cc = v cc max, v ccq = v ccq max using standard word/byte single reads device is enabled (see table 2, chip enable truth table ) f = 33 mhz, i out = 0 ma tbd tbd ma ttl inputs,v cc = v cc max, v ccq = v ccq max using standard word/byte single reads device is enabled (see table 2, chip enable truth table ) f = 33 mhz, i out = 0 ma
28f128j3a, 28F640J3A, 28f320j3a product preview 43 dc characteristics, continued notes: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (packages and speeds). contact intels application support hotline or your local sales office for information about typical specifications. 2. i ccws and i cces are specified with the device de-selected. if the device is read or written while in erase suspend mode, the devices current draw is i ccr or i ccw . 3. includes sts. 4. block erases, programming, and lock-bit configurations are inhibited when v pen v penlk , and not guaranteed in the range between v penlk (max) and v penh (min), and above v penh (max). 5. cmos inputs are either v cc 0.2 v or gnd 0.2 v. ttl inputs are either v il or v ih . 6. sampled, not 100% tested. 7. block erases, programming, and lock-bit configurations are inhibited when v cc < v lko , and not guaranteed in the range between v lko (min) and v cc (min), and above v cc (max). 8. typically, v pen is connected to v cc (2.7 vC3.6 v). 9. current values are specified over the commercial temperature range (0 c to 70 c) and may increase slightly at C20 c. i ccw v cc program or set lock-bit current 1,6,9 35 60 ma cmos inputs, v pen = v cc 40 70 ma ttl inputs, v pen = v cc i cce v cc block erase or clear block lock-bits current 1,6,9 35 70 ma cmos inputs, v pen = v cc 40 80 ma ttl inputs, v pen = v cc i ccws i cces v cc program suspend or block erase suspend current 1,2,9 10 ma device is disabled (see table 2, chip enable truth table ) symbol parameter notes min max unit test conditions v il input low voltage 6 C0.5 0.8 v v ih input high voltage 6 2.0 v ccq + 0.5 v v ol output low voltage 3,6 0.45 v v ccq = v ccq1 min i ol = 5.8 ma 0.4 v v ccq = v ccq2/3 min i ol = 2 ma 0.2 v v ccq = v ccq2/3 min i ol = 100 a v oh output high voltage 3,6 2.4 v v ccq = v ccq1 min or v ccq = v ccq2 min i oh = C2.5 ma (v ccq1 ) = C2 ma (v ccq2/3 ) 0.85 v ccq v v ccq = v ccq min i oh = C2.5 ma v ccq C 0.2 v v ccq = v ccq min i oh = C100 a v penlk v pen lockout during program, erase and lock-bit operations 4,6,8 0.8 v v penh v pen during block erase, program, or lock-bit operations 4,8 2.7 3.6 v v lko v cc lockout voltage 7 2.0 v symbol parameter notes typ max unit test conditions
28f128j3a, 28F640J3A, 28f320j3a 44 product preview note: ac test inputs are driven at v oh (2.4 v ttl ) for a logic "1" and v ol (0.45 v ttl ) for a logic "0." input timing begins at v ih (2.0 v ttl ) and v il (0.8 v ttl ). output timing ends at v ih and v il . input rise and fall times (10% to 90%) <10 ns. note: ac test inputs are driven at v ccq for a logic "1" and 0.0 v for a logic "0." input timing begins, and output timing ends, at v ccq /2 v (50% of v ccq ). input rise and fall times (10% to 90%) < 5 ns. note: c l includes jig capacitance figure 15. transient input/output reference waveform for v ccq = 5.0 v 10% output test points input 2.0 0.8 2.0 0.8 2.4 0.45 figure 16. transient input/output reference waveform for v ccq = 3.0 vC3.6 v or v ccq = 2.7 vC3.6 v output test points input v ccq /2 v ccq 0.0 v ccq /2 figure 17. transient equivalent testing load circuit device under test out r l = 3.3 k w 1n914 1.3v c l test configuration c l (pf) v ccq = 5.0 v 10%; v cc = 2.7 v - 3.6 v 30 v ccq = v cc = 3.0 v - 3.6 v 30 v ccq = v cc = 2.7 v - 3.6 v 30
28f128j3a, 28F640J3A, 28f320j3a product preview 45 6.5 ac characteristics read-only operations (1,2) versions (all units in ns unless otherwise noted) v cc 3.0 vC3.6 v (4) 2.7 vC3.6 v (4) 2.7 vC3.6 v (4) v ccq 3.0 vC3.6 v (4) 2.7 vC3.6 v (4) 5.0 vC3.6 v (4) # sym parameter notes min max min max min max r1 t avav read/write cycle time 32 mbit 100 100 120 64 mbit 120 120 150 128 mbit 150 150 180 r2 t avqv address to output delay 32 mbit 100 100 100 64 mbit 120 120 150 128 mbit 150 150 180 r3 t elqv ce x to output delay 32 mbit 2 100 100 130 64 mbit 2 120 120 150 128 mbit 2 150 150 180 r4 t glqv oe# to non-array output delay 2, 6 50 50 80 r5 t phqv rp# high to output delay 32 mbit 150 150 180 64 mbit 180 180 210 128 mbit 210 210 240 r6 t elqx ce x to output in low z 3 0 0 0 r7 t glqx oe# to output in low z 3 0 0 0 r8 t ehqz ce x high to output in high z 3 55 55 85 r9 t ghqz oe# high to output in high z 3 15 15 45 r10 t oh output hold from address, ce x , or oe# change, whichever occurs first 30 0 0 r11 t elfl t elfh ce x low to byte# high or low 3 10 10 40 r12 t flqv t fhqv byte# to output delay 1000 1000 1030 r13 t flqz byte# to output in high z 3 1000 1000 1030 r14 t ehel cex high to cex low 3 0 0 0 r15 t apa page address access time 3, 5 25 30 60 r16 t glqv oe# to array output delay 6 25 30 60
28f128j3a, 28F640J3A, 28f320j3a 46 product preview notes: ce x low is defined as the first edge of ce 0 , ce 1 , or ce 2 that enables the device. ce x high is defined at the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). 1. see ac input/output reference waveforms for the maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the first edge of ce 0 , ce 1 , or ce 2 that enables the device (see table 2, chip enable truth table ) without impact on t elqv . 3. sampled, not 100% tested. 4. see figures 14C16, transient input/output reference waveform for v ccq = 5.0 v 10%, transient input/ output reference waveform for v ccq = 3.0 v C3.6 v or v ccq = 2.7 v C3.6 v, and transient equivalent testing load circuit for testing characteristics. 5. for devices configured to standard word/byte read mode, r15 (t apa ) will equal r2 (t avqv ). 6. when reading the flash array a faster t glqv (r16) applies. non-array reads refer to status register reads, query reads, or device identifier reads. 0606_16 note: ce x low is defined as the first edge of ce 0 , ce 1 , or ce 2 that enables the device. ce x high is defined at the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). for standard word/byte read operations, r15 (t apa ) will equal r2 (t avqv ). when reading the flash array a faster t glqv (r16) applies. non-array reads refer to status register reads, query reads, or device identifier reads. figure 18. ac waveform for both page-mode and standard word/byte read operations r1 r8 r10 high z r13 r11 r12 r6 r5 r4 or r16 r3 r7 r2 r9 valid output addresses [a 23 -a 3 ] v ih v il v ih v il disabled (v ih ) enabled (v il ) ce x [e] v ih v il v oh v ol v ih v il v ih v il v ih v il oe# [g] we# [w] data [d/q] dq 0 -dq 15 v cc rp# [p] byte# [f] high z r14 v ih v il addresses [a 2 -a 0 ] v ih v il v ih v il valid output r15 valid output valid address valid address valid address valid output valid address
28f128j3a, 28F640J3A, 28f320j3a product preview 47 6.6 ac characteristics write operations (1,2) notes: ce x low is defined as the first edge of ce 0 , ce 1 , or ce 2 that enables the device. ce x high is defined at the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). 1. read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during read-only operations. refer to ac characteristicsCread-only operations . 2. a write operation can be initiated and terminated with either ce x or we#. 3. sampled, not 100% tested. 4. refer to table 4 for valid a in and d in for block erase, program, or lock-bit configuration. 5. sts timings are based on sts configured in its ry/by# default mode. 6. for array access, t avqv is required in addition to t whgl for any accesses after a write. 7. v pen should be held at v penh until determination of block erase, program, or lock-bit configuration success (sr.1/3/4/5 = 0). 8. write pulse width (t wp ) is defined from ce x or we# going low (whichever goes low first) to ce x or we# going high (whichever goes high first). hence, t wp = t wlwh = t eleh = t wleh = t elwh . if ce x is driven low 10 ns before we# going low, we# pulse width requirement decreases to t wp - 10 ns. 9. write pulse width high (t wph ) is defined from ce x or we# going high (whichever goes high first) to ce x or we# going low (whichever goes low first). hence, t wph = t whwl = t ehel = t whel = t ehwl . versions valid for all speeds unit # symbol parameter notes min max w1 t phwl ( t phel ) rp# high recovery to we# (ce x ) going low 3 1 s w2 t elwl (t wlel )ce x (we#) low to we# (ce x ) going low 8 0 ns w3 t wp write pulse width 8 70 ns w4 t dvwh ( t dveh ) data setup to we# (ce x ) going high 4 50 ns w5 t avwh ( t aveh ) address setup to we# (ce x ) going high 4 50 ns w6 t wheh ( t ehwh ) ce x (we#) hold from we# (ce x ) high 10 ns w7 t whdx ( t ehdx ) data hold from we# (ce x ) high 0 ns w8 t whax ( t ehax ) address hold from we# (ce x ) high 0 ns w9 t wph write pulse width high 9 30 ns w10 t phhwh ( t phheh ) rp# v hh setup to we# (ce x ) going high 3 0 ns w11 t vpwh ( t vpeh ) v pen setup to we# (ce x ) going high 3 0 ns w12 t whgl ( t ehgl ) write recovery before read 6 35 ns w13 t whrl ( t ehrl ) we# (ce x ) high to sts going low 5 90 ns w14 t qvph rp# v hh hold from valid srd, sts going high 3,5,7 0 ns w15 t qvvl v pen hold from valid srd, sts going high 3,5,7 0 ns
28f128j3a, 28F640J3A, 28f320j3a 48 product preview 0606_17 notes: ce x low is defined as the first edge of ce 0 , ce 1 , or ce 2 that enables the device. ce x high is defined at the first edge of ce 0 , ce 1 , or ce 2 that disables the device (see table 2, chip enable truth table ). sts is shown in its default mode (ry/by#). a. v cc power-up and standby. b. write block erase, write buffer, or program setup. c. write block erase or write buffer confirm, or valid address and data. d. automated erase delay. e. read status register or query data. f. write read array command. figure 19. ac waveform for write operations a in a in ab c d e f w15 d in w11 w10 valid srd d in d in w13 w14 w7 w3 w4 high z w2 w9 w16 w12 w6 w1 w5 w8 v ih v il addresses [a] disabled (v ih ) enabled (v il ) ce x , (we#) [e(w)] v ih v il oe# [g] disabled (v ih ) enabled (v il ) we#, (ce x ) [w(e)] v ih v il data [d/q] v oh v ol sts [r] v ih v il rp# [p] v penlk v il v pen [v] v penh v hh
28f128j3a, 28F640J3A, 28f320j3a product preview 49 0606_18 note: sts is shown in its default mode (ry/by#). notes: 1. these specifications are valid for all product versions (packages and speeds). 2. if rp# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the minimum required rp# pulse low time is 100 ns. 3. a reset time, t phqv , is required from the latter of sts (in ry/by# mode) or rp# going high until outputs are valid. figure 20. ac waveform for reset operation ih v il v rp# (p) ih v il v sts (r) p1 p2 reset specifications (1) # sym parameter notes min max unit p1 t plph rp# pulse low time (if rp# is tied to v cc , this specification is not applicable) 235 s p2 t phrh rp# high to reset during block erase, program, or lock-bit configuration 3 100 ns
28f128j3a, 28F640J3A, 28f320j3a 50 product preview 6.7 block erase, program, and lock-bit configuration performance (3,4) notes: 1. typical values measured at t a = +25 c and nominal voltages. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. these performance numbers are valid for all speed versions. 4. sampled but not 100% tested. 5. these values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. effective per-byte program time (t whqv1 , t ehqv1 ) is 6.3 s/byte (typical) 7. effective per-word program time (t whqv2 , t ehqv2 ) is 12.6 s/word (typical) # sym parameter notes min max unit w16 write buffer byte program time (time to program 32 bytes/16 words) 2,5,6,7 200 tbd s w16 t whqv3 t ehqv3 byte program time (using word/byte program command) 2 180 tbd s block program time (using write to buffer command) 2 0.8 tbd sec w16 t whqv4 t ehqv4 block erase time 2 0.7 tbd sec w16 t whqv5 t ehqv5 set lock-bit time 2 32 tbd s w16 t whqv6 t ehqv6 clear block lock-bits time 2 0.3 tbd sec w16 t whrh1 t ehrh1 program suspend latency time to read 25 30 s w16 t whrh t ehrh erase suspend latency time to read 26 35 s
28f128j3a, 28F640J3A, 28f320j3a product preview 51 7.0 ordering information note: 1. these speeds are for either the standard asynchronous read access times or for the first access of a page- mode read sequence. valid combinations r c 2 8 f 1 2 8 j 3 - 1 5 0 package e = 56-lead tsop rc = 64-ball easy bga product line designator for all intel? flash products access speed (ns) (1) 128 mbit = 150 64 mbit = 120 32 mbit = 100 product family j = intel strataflash tm memory, 2 bits-per-cell device density 128 = x8/x16 (128 mbit) 640 = x8/x16 (64 mbit) 320 = x8/x16 (32 mbit) voltage (v cc /v pen ) 3 = 3v/3v a intel? 0.25 micron etox? vi process technology 56-lead tsop 64-ball easy bga e28f128j3a-150 rc28f128j3a-150 e28F640J3A-120 rc28F640J3A-120 e28f3203a-100 rc28f3203a-100
28f128j3a, 28F640J3A, 28f320j3a 52 product preview 8.0 additional information (1,2) note: 1. please call the intel literature center at (800) 548-4725 to request intel documentation. international customers should contact their local intel or distribution sales office. 2. visit intels world wide web home page at http://www.intel.com for technical documentation and tools. 3. for the most current information on intel strataflash memory, visit our website at http://developer.intel.com/ design/flash/isf. 4. this document is available on the web at http://developer.intel.com/design/flcomp/packdata/298049.htm. order number document/tool 298130 3 volt intel ? strataflash? memory 128-, 64-, 32-mbit specification update 210830 flash memory databook 290668 intel? persistent storage manager datasheet 292237 ap-689 using intel? persistent storage manager note 3 ap-707 3 volt intel ? strataflash? memory cpu interface design guide 290606 5 volt intel ? strataflash? memoryi28f320j5 and 28f640j5 datasheet 290608 3 volt flashfile? memory; 28f160s3 and 28f320s3 datasheet 290609 5 volt flashfile? memory; 28f160s5 and 28f320s5 datasheet 290429 5 volt flashfile? memory; 28f008sa datasheet 290598 3 volt flashfile? memory; 28f004s3, 28f008s3, 28f016s3 datasheet 290597 5 volt flashfile? memory; 28f004s5, 28f008s5, 28f016s5 datasheet 297859 ap-677 intel ? strataflash? memory technology 292222 ap-664 designing intel ? strataflash? memory into intel ? architecture 292221 ap-663 using the intel ? strataflash? memory write buffer 292218 ap-660 migration guide to 3 volt intel ? strataflash? memory 292205 ap-647 5 volt intel ? strataflash? memory design guide 292204 ap-646 common flash interface (cfi) and command sets 292202 ap-644 migration guide to 5 volt intel ? strataflash? memory 297846 comprehensive users guide for bga* packages note 4 preliminary mechanical specification for easy bga package

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